A real-time 256 × 256 point two-dimensional FFT single-chip processor

Hiroshi Miyanaga, Hironori Yamauchi, Kazuhiro Matsuda

研究成果: Conference contribution査読

4 被引用数 (Scopus)

抄録

A single-chip 400-MFLOPS 2-D FFT processor VLSI architecture designed using 0.8-μm CMOS technology is proposed. This processor integrates 380,000 transistors in an area of 11.58 × 11.58 mm2 with a typical machine cycle time of 25 ns. The 24-bit floating point processor executes 2n × 2n point 2-D FFT in real time, e.g., 256 × 256 point FFT is executed in 14 ms. This excellent performance in terms of speed and dynamic range makes the real-time processing practical for video as well as speech processing.

本文言語English
ホスト出版物のタイトルProceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing
編集者 Anon
出版社Publ by IEEE
ページ1193-1196
ページ数4
ISBN(印刷版)078030033
出版ステータスPublished - 1 12月 1991
イベントProceedings of the 1991 International Conference on Acoustics, Speech, and Signal Processing - ICASSP 91 - Toronto, Ont, Can
継続期間: 14 5月 199117 5月 1991

出版物シリーズ

名前Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing
2
ISSN(印刷版)0736-7791

Conference

ConferenceProceedings of the 1991 International Conference on Acoustics, Speech, and Signal Processing - ICASSP 91
CityToronto, Ont, Can
Period14/05/9117/05/91

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