@inproceedings{33033385c97142118b307b2ca7745a8c,
title = "A real-time 256 × 256 point two-dimensional FFT single-chip processor",
abstract = "A single-chip 400-MFLOPS 2-D FFT processor VLSI architecture designed using 0.8-μm CMOS technology is proposed. This processor integrates 380,000 transistors in an area of 11.58 × 11.58 mm2 with a typical machine cycle time of 25 ns. The 24-bit floating point processor executes 2n × 2n point 2-D FFT in real time, e.g., 256 × 256 point FFT is executed in 14 ms. This excellent performance in terms of speed and dynamic range makes the real-time processing practical for video as well as speech processing.",
author = "Hiroshi Miyanaga and Hironori Yamauchi and Kazuhiro Matsuda",
year = "1991",
month = dec,
day = "1",
language = "English",
isbn = "078030033",
series = "Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing",
publisher = "Publ by IEEE",
pages = "1193--1196",
editor = "Anon",
booktitle = "Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing",
note = "Proceedings of the 1991 International Conference on Acoustics, Speech, and Signal Processing - ICASSP 91 ; Conference date: 14-05-1991 Through 17-05-1991",
}