経営学研究科

  • 17 Article
  • 4 Conference contribution
  • 2 Chapter
  • 2 Review article
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Conference contribution

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  • 1991

    A real-time 256 × 256 point two-dimensional FFT single-chip processor

    Miyanaga, H., Yamauchi, H. & Matsuda, K., 1 12月 1991, Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing. Anon (ed.). Publ by IEEE, p. 1193-1196 4 p. (Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing; vol. 2).

    研究成果: Conference contribution › 査読

    4 被引用数 (Scopus)
  • 1984

    0. 85 ns 1Kb BIPOLAR ECL RAM.

    Miyanaga, H., Konaka, S., Yamamoto, Y. & Sakai, T., 1 12月 1984, Conference on Solid State Devices and Materials. Business Cent for Academic Soc Japan, p. 225-228 4 p. (Conference on Solid State Devices and Materials).

    研究成果: Conference contribution › 査読

    18 被引用数 (Scopus)

  • 1. 1 NS ACCESS TIME 4 KB BIPOLAR RAM USING SUPER SELF-ALIGNED TECHNOLOGY.

    Miyanaga, H., Kobayashi, Y., Konaka, S., Yamamoto, Y. & Sakai, T., 1 12月 1984, Digest of Technical Papers - Symposium on VLSI Technology. Business Cent for Academic Soc Japan, p. 50-51 2 p. (Digest of Technical Papers - Symposium on VLSI Technology).

    研究成果: Conference contribution › 査読

    8 被引用数 (Scopus)
  • 1983

    1. 5 NSEC 1K BIT BIPOLAR RAM.

    Yamamoto, Y., Miyanaga, H. & Sakai, T., 1 12月 1983, European Solid-State Circuits Conference. Presses Polytechniques Romandes, p. 93-96 4 p. (European Solid-State Circuits Conference).

    研究成果: Conference contribution › 査読

    2 被引用数 (Scopus)