A 0.2μm-gate buried p-layer MESFET using a new gate fabrication technique is reported. With this technique, the gate length can be easily reduced down to less than 0.2μm. The source resistance of enhancement mode FET can be also reduced resulting in excellent DC and RF performances. The maximum transconductance of 648mS/mm at a gate voltage of 0.6V and K-value of 506mS/Vmm were obtained. The maximum cut-off frequency was as high as 96.1GHz. The propagation delay time of 8.1ps/gate was observed with a power dissipation of 1.7mW/gate at a supply voltage of 1V.
|Number of pages||4|
|Publication status||Published - 1 Dec 1990|
|Event||22nd International Conference on Solid State Devices and Materials - Sendai, Jpn|
Duration: 22 Aug 1990 → 24 Aug 1990
|Conference||22nd International Conference on Solid State Devices and Materials|
|Period||22/08/90 → 24/08/90|