Sub-10 ps/gate DCFL circuit with 0.2 μm-gate GaAs MESFET

Hiromi Tsuji, Hiroki I. Fujishiro, Hiroshi Nakamura, Seiji Nishi

Research output: Contribution to conferencePaper

Abstract

A 0.2μm-gate buried p-layer MESFET using a new gate fabrication technique is reported. With this technique, the gate length can be easily reduced down to less than 0.2μm. The source resistance of enhancement mode FET can be also reduced resulting in excellent DC and RF performances. The maximum transconductance of 648mS/mm at a gate voltage of 0.6V and K-value of 506mS/Vmm were obtained. The maximum cut-off frequency was as high as 96.1GHz. The propagation delay time of 8.1ps/gate was observed with a power dissipation of 1.7mW/gate at a supply voltage of 1V.

Original languageEnglish
Pages83-86
Number of pages4
Publication statusPublished - 1 Dec 1990
Event22nd International Conference on Solid State Devices and Materials - Sendai, Jpn
Duration: 22 Aug 199024 Aug 1990

Conference

Conference22nd International Conference on Solid State Devices and Materials
CitySendai, Jpn
Period22/08/9024/08/90

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Tsuji, H., Fujishiro, H. I., Nakamura, H., & Nishi, S. (1990). Sub-10 ps/gate DCFL circuit with 0.2 μm-gate GaAs MESFET. 83-86. Paper presented at 22nd International Conference on Solid State Devices and Materials, Sendai, Jpn, .