SPRAM (SPin-transfer torque RAM) design and its impact on digital systems

Takayuki Kawahara, R. Takemura, H. Takahashi, H. Ohno

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

To demonstrate circuit technologies for potential low-power non-volatile RAM, or universal memory, we fabricated a 1.8V 2-Mb SPRAM (SPin-transfer torque RAM) chip using a 0.2-μm logic process with a MgO tunneling barrier cell. This chip features an array scheme with bit-by-bit bidirectional current writing to enable proper spin-transfer torque writing and parallel-direction current reading for preventing read disturbance. In addition, this memory can improve the power efficiency of digital equipment.

Original languageEnglish
Title of host publicationICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems
Pages1011-1014
Number of pages4
DOIs
Publication statusPublished - 1 Dec 2007
Event14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 - Marrakech, Morocco
Duration: 11 Dec 200714 Dec 2007

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

Conference14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
CountryMorocco
CityMarrakech
Period11/12/0714/12/07

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Kawahara, T., Takemura, R., Takahashi, H., & Ohno, H. (2007). SPRAM (SPin-transfer torque RAM) design and its impact on digital systems. In ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems (pp. 1011-1014). [4511164] (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). https://doi.org/10.1109/ICECS.2007.4511164