HIGH SPEED INVERTED-HEMT LOGIC WITH A SUB-HALF-MICRON GATE.

T. Saito, Hiroki Fujishiro, S. Nishi, Y. Sano, K. Kaminishi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A short gate length inverted HEMT using a new gate fabrication technique is reported. The photoresist opening for gate formation was narrowed by evaporated Ti at a small angle. By using this technique, not only the gate length was reduced but also the Schottky characteristics were improved. The uniformity of threshold voltage was not degraded. A 0. 28 mu m gate I-HEMT was fabricated and a small drain conductance of 13mS/mm was observed. A minimum propagation delay time of 11. 9psec/gate with a power dissipation of 0. 560m/gate was obtained for a 0. 5 mu m DCFL ring oscillator at room temperature.

Original languageEnglish
Title of host publicationConference on Solid State Devices and Materials
PublisherJapan Soc of Applied Physics
Pages267-270
Number of pages4
ISBN (Print)4930813212
Publication statusPublished - 1 Dec 1987

Publication series

NameConference on Solid State Devices and Materials

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Saito, T., Fujishiro, H., Nishi, S., Sano, Y., & Kaminishi, K. (1987). HIGH SPEED INVERTED-HEMT LOGIC WITH A SUB-HALF-MICRON GATE. In Conference on Solid State Devices and Materials (pp. 267-270). (Conference on Solid State Devices and Materials). Japan Soc of Applied Physics.