High speed digital smart image sensor with image compression function

Sousuke Narisawa, Kentaro Masuda, Takayuki Hamamoto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

We propose a high speed digital smart image sensor on which A/D conversion circuits and digital processing circuits of image compression are integrated. By on-sensor image compression, the proposed sensor can overcome a communication bottle neck between a sensor and peripherals that is one of the most serious problems for achieving high frame rates. The compression method uses the correlation between two consecutive frames. It has some compression modes by controlling spatial and temporal resolutions. In this paper, the algorithm of on-sensor-compression is explained and some experimental results are shown. Finally, we show the design of new digital smart sensor.

Original languageEnglish
Title of host publicationProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
Pages128-131
Number of pages4
Publication statusPublished - 1 Dec 2004
EventProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits - Fukuoka, Japan
Duration: 4 Aug 20045 Aug 2004

Publication series

NameProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

Conference

ConferenceProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
CountryJapan
CityFukuoka
Period4/08/045/08/04

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Narisawa, S., Masuda, K., & Hamamoto, T. (2004). High speed digital smart image sensor with image compression function. In Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (pp. 128-131). [7-5] (Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits).