Focal plane compression 128×128 image sensor based on column parallel architecture

Takayuki Hamamoto; Yasuhiro Ohtsuka; Kiyoharu Aizawa

doi:10.1117/12.324001

Focal plane compression 128×128 image sensor based on column parallel architecture

Takayuki Hamamoto, Yasuhiro Ohtsuka, Kiyoharu Aizawa

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

Abstract

In order to enhance the performance of image sensing, we have been investigating a novel image sensor which compresses image signal on the sensor focal plane. By the integration of sensing and compression, number of pixels in the image signal that has to be readout from the sensor can be significantly reduced, and the integration can consequently increase the pixel rate of the sensor. In this paper, we describe a new prototype sensor based on a column parallel architecture which has 128×128 pixels. We have improved the processing circuits of the new prototype to achieve much lower power dissipation and higher processing speed. We have verified that the processing circuits can be operated at 5000 frames /second.

Original language	English
Pages (from-to)	222-229
Number of pages	8
Journal	Proceedings of SPIE - The International Society for Optical Engineering
Volume	3410
DOIs	https://doi.org/10.1117/12.324001
Publication status	Published - 1998
Event	Advanced Focal Plane Arrays and Electronic Cameras II - Zurich, Switzerland Duration: 18 May 1998 → 19 May 1998

Keywords

Column parallel architecture
Computational sensor
Conditional replenishment
Image compression
Smart sensor

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10.1117/12.324001

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title = "Focal plane compression 128×128 image sensor based on column parallel architecture",

abstract = "In order to enhance the performance of image sensing, we have been investigating a novel image sensor which compresses image signal on the sensor focal plane. By the integration of sensing and compression, number of pixels in the image signal that has to be readout from the sensor can be significantly reduced, and the integration can consequently increase the pixel rate of the sensor. In this paper, we describe a new prototype sensor based on a column parallel architecture which has 128×128 pixels. We have improved the processing circuits of the new prototype to achieve much lower power dissipation and higher processing speed. We have verified that the processing circuits can be operated at 5000 frames /second.",

keywords = "Column parallel architecture, Computational sensor, Conditional replenishment, Image compression, Smart sensor",

author = "Takayuki Hamamoto and Yasuhiro Ohtsuka and Kiyoharu Aizawa",

year = "1998",

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language = "English",

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journal = "Proceedings of SPIE - The International Society for Optical Engineering",

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AU - Hamamoto, Takayuki

AU - Ohtsuka, Yasuhiro

AU - Aizawa, Kiyoharu

PY - 1998

Y1 - 1998

N2 - In order to enhance the performance of image sensing, we have been investigating a novel image sensor which compresses image signal on the sensor focal plane. By the integration of sensing and compression, number of pixels in the image signal that has to be readout from the sensor can be significantly reduced, and the integration can consequently increase the pixel rate of the sensor. In this paper, we describe a new prototype sensor based on a column parallel architecture which has 128×128 pixels. We have improved the processing circuits of the new prototype to achieve much lower power dissipation and higher processing speed. We have verified that the processing circuits can be operated at 5000 frames /second.

AB - In order to enhance the performance of image sensing, we have been investigating a novel image sensor which compresses image signal on the sensor focal plane. By the integration of sensing and compression, number of pixels in the image signal that has to be readout from the sensor can be significantly reduced, and the integration can consequently increase the pixel rate of the sensor. In this paper, we describe a new prototype sensor based on a column parallel architecture which has 128×128 pixels. We have improved the processing circuits of the new prototype to achieve much lower power dissipation and higher processing speed. We have verified that the processing circuits can be operated at 5000 frames /second.

KW - Column parallel architecture

KW - Computational sensor

KW - Conditional replenishment

KW - Image compression

KW - Smart sensor

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JO - Proceedings of SPIE - The International Society for Optical Engineering

JF - Proceedings of SPIE - The International Society for Optical Engineering

T2 - Advanced Focal Plane Arrays and Electronic Cameras II

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ER -

Focal plane compression 128×128 image sensor based on column parallel architecture

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Keywords

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