Circuit Optimization of Ternary Sparse Neural Net

Taichi Megumi, Takayuki Kawahara

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In the coming years, AIoT, which combines AI and IoT, is expected to become a reality. To realize it, an AI chip with small size, high speed, and high recognition accuracy is required. Binarized Neural Networks (BNNs), a binarization method, are known for miniaturization. Ternary Sparse XNOR-Net (TSXN), a ternary method, is expected to significantly reduce the circuit size while improving recognition accuracy compared with BNN. In this study, we proposed a further circuit optimization method for TSXN and evaluated its implementation on an FPGA. Compared with BNN, the proposed method reduced the circuit size by 81.0% and increased the operation speed by 33.3%, while improving the recognition accuracy by 3.7%.

Original languageEnglish
Title of host publication2024 IEEE 22nd World Symposium on Applied Machine Intelligence and Informatics, SAMI 2024 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages53-58
Number of pages6
ISBN (Electronic)9798350317206
DOIs
Publication statusPublished - 2024
Event2024 IEEE 22nd World Symposium on Applied Machine Intelligence and Informatics, SAMI 2024 - Stara Lesna, Slovakia
Duration: 25 Jan 202427 Jan 2024

Publication series

Name2024 IEEE 22nd World Symposium on Applied Machine Intelligence and Informatics, SAMI 2024 - Proceedings

Conference

Conference2024 IEEE 22nd World Symposium on Applied Machine Intelligence and Informatics, SAMI 2024
Country/TerritorySlovakia
CityStara Lesna
Period25/01/2427/01/24

Keywords

  • Deep Learning
  • FPGA
  • Neural Network
  • Sparse
  • Ternary

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