A real-time 256 × 256 point two-dimensional FFT single-chip processor

Hiroshi Miyanaga, Hironori Yamauchi, Kazuhiro Matsuda

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Citations (Scopus)

Abstract

A single-chip 400-MFLOPS 2-D FFT processor VLSI architecture designed using 0.8-μm CMOS technology is proposed. This processor integrates 380,000 transistors in an area of 11.58 × 11.58 mm2 with a typical machine cycle time of 25 ns. The 24-bit floating point processor executes 2n × 2n point 2-D FFT in real time, e.g., 256 × 256 point FFT is executed in 14 ms. This excellent performance in terms of speed and dynamic range makes the real-time processing practical for video as well as speech processing.

Original languageEnglish
Title of host publicationProceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing
Editors Anon
PublisherPubl by IEEE
Pages1193-1196
Number of pages4
ISBN (Print)078030033
Publication statusPublished - 1 Dec 1991
EventProceedings of the 1991 International Conference on Acoustics, Speech, and Signal Processing - ICASSP 91 - Toronto, Ont, Can
Duration: 14 May 199117 May 1991

Publication series

NameProceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing
Volume2
ISSN (Print)0736-7791

Conference

ConferenceProceedings of the 1991 International Conference on Acoustics, Speech, and Signal Processing - ICASSP 91
CityToronto, Ont, Can
Period14/05/9117/05/91

Fingerprint

Dive into the research topics of 'A real-time 256 × 256 point two-dimensional FFT single-chip processor'. Together they form a unique fingerprint.

Cite this