A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions

T. Ishigaki, T. Kawahara, R. Takemura, K. Ono, K. Ito, H. Matsuoka, H. Ohno

Research output: Chapter in Book/Report/Conference proceedingConference contribution

82 Citations (Scopus)

Abstract

We first report a multi-level-cell (MLC) spin-transfer torque memory (SPRAM) with series-connected magnetotunnel junctions (MTJs). The series MTJs (with different areas) show multi-level resistances by a combination of their magnetization directions. A four-level operation by spin-transfer-torque writing was experimentally demonstrated. A scheme for the write/read operation of the MLC SPRAM was also presented. Keywords: MRAM, SPRAM, spin, multi-bit, and MLC.

Original languageEnglish
Title of host publication2010 Symposium on VLSI Technology, VLSIT 2010
Pages47-48
Number of pages2
DOIs
Publication statusPublished - 19 Oct 2010
Event2010 Symposium on VLSI Technology, VLSIT 2010 - Honolulu, HI, United States
Duration: 15 Jun 201017 Jun 2010

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Conference

Conference2010 Symposium on VLSI Technology, VLSIT 2010
CountryUnited States
CityHonolulu, HI
Period15/06/1017/06/10

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Ishigaki, T., Kawahara, T., Takemura, R., Ono, K., Ito, K., Matsuoka, H., & Ohno, H. (2010). A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions. In 2010 Symposium on VLSI Technology, VLSIT 2010 (pp. 47-48). [5556126] (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2010.5556126