A-40-dBc Integrated-Phase-Noise 45-GHz Sub-Sampling PLL with 3.9-dBm Output and 2.1% DC-to-RF Efficiency

Sangyeop Lee, Kyoya Takano, Shinsuke Hara, Ruibing Dong, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a millimeter-wave (mmW) sub-sampling PLL in 40 nm CMOS. Sub-sampling PLL reduces the in-band phase noise due to the charge pump lower than the ordinary N2× when frequency is multiplied by N. Two sub-sampling phase detectors (SSPD) and charge pumps (SSCP) are employed to cancel mixing products due to sub-sampling around the VCO output tone and to enhance loop gain. The out-of-band phase noise, dictated by the VCO phase noise, is reduced by employing a VCO consisting of transmission-line resonators, large MOSFET switches, and inverse-class-F output matching. The proposed PLL, operating at 45 GHz, achieves-40-dBc integrated phase noise (0.1 kHz-40 MHz), 3.9-dBm output power, and 2.1% DC-to-RF efficiency.

Original languageEnglish
Title of host publication2019 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages175-178
Number of pages4
ISBN (Electronic)9781728117010
DOIs
Publication statusPublished - Jun 2019
Event2019 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2019 - Boston, United States
Duration: 2 Jun 20194 Jun 2019

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Volume2019-June
ISSN (Print)1529-2517

Conference

Conference2019 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2019
CountryUnited States
CityBoston
Period2/06/194/06/19

Fingerprint

Phase locked loops
Phase noise
Variable frequency oscillators
Sampling
Pumps
Millimeter waves
Resonators
Electric lines
Switches
Detectors

Keywords

  • CMOS
  • Sub-sampling
  • energy efficient
  • low phase noise
  • phase-locked loop

Cite this

Lee, S., Takano, K., Hara, S., Dong, R., Amakawa, S., Yoshida, T., & Fujishima, M. (2019). A-40-dBc Integrated-Phase-Noise 45-GHz Sub-Sampling PLL with 3.9-dBm Output and 2.1% DC-to-RF Efficiency. In 2019 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2019 (pp. 175-178). [8701745] (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium; Vol. 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RFIC.2019.8701745
Lee, Sangyeop ; Takano, Kyoya ; Hara, Shinsuke ; Dong, Ruibing ; Amakawa, Shuhei ; Yoshida, Takeshi ; Fujishima, Minoru. / A-40-dBc Integrated-Phase-Noise 45-GHz Sub-Sampling PLL with 3.9-dBm Output and 2.1% DC-to-RF Efficiency. 2019 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 175-178 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).
@inproceedings{a90d728247d94ca0b39ae338ffae35e4,
title = "A-40-dBc Integrated-Phase-Noise 45-GHz Sub-Sampling PLL with 3.9-dBm Output and 2.1{\%} DC-to-RF Efficiency",
abstract = "This paper presents a millimeter-wave (mmW) sub-sampling PLL in 40 nm CMOS. Sub-sampling PLL reduces the in-band phase noise due to the charge pump lower than the ordinary N2× when frequency is multiplied by N. Two sub-sampling phase detectors (SSPD) and charge pumps (SSCP) are employed to cancel mixing products due to sub-sampling around the VCO output tone and to enhance loop gain. The out-of-band phase noise, dictated by the VCO phase noise, is reduced by employing a VCO consisting of transmission-line resonators, large MOSFET switches, and inverse-class-F output matching. The proposed PLL, operating at 45 GHz, achieves-40-dBc integrated phase noise (0.1 kHz-40 MHz), 3.9-dBm output power, and 2.1{\%} DC-to-RF efficiency.",
keywords = "CMOS, Sub-sampling, energy efficient, low phase noise, phase-locked loop",
author = "Sangyeop Lee and Kyoya Takano and Shinsuke Hara and Ruibing Dong and Shuhei Amakawa and Takeshi Yoshida and Minoru Fujishima",
year = "2019",
month = "6",
doi = "10.1109/RFIC.2019.8701745",
language = "English",
series = "Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "175--178",
booktitle = "2019 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2019",

}

Lee, S, Takano, K, Hara, S, Dong, R, Amakawa, S, Yoshida, T & Fujishima, M 2019, A-40-dBc Integrated-Phase-Noise 45-GHz Sub-Sampling PLL with 3.9-dBm Output and 2.1% DC-to-RF Efficiency. in 2019 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2019., 8701745, Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, vol. 2019-June, Institute of Electrical and Electronics Engineers Inc., pp. 175-178, 2019 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2019, Boston, United States, 2/06/19. https://doi.org/10.1109/RFIC.2019.8701745

A-40-dBc Integrated-Phase-Noise 45-GHz Sub-Sampling PLL with 3.9-dBm Output and 2.1% DC-to-RF Efficiency. / Lee, Sangyeop; Takano, Kyoya; Hara, Shinsuke; Dong, Ruibing; Amakawa, Shuhei; Yoshida, Takeshi; Fujishima, Minoru.

2019 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 175-178 8701745 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium; Vol. 2019-June).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A-40-dBc Integrated-Phase-Noise 45-GHz Sub-Sampling PLL with 3.9-dBm Output and 2.1% DC-to-RF Efficiency

AU - Lee, Sangyeop

AU - Takano, Kyoya

AU - Hara, Shinsuke

AU - Dong, Ruibing

AU - Amakawa, Shuhei

AU - Yoshida, Takeshi

AU - Fujishima, Minoru

PY - 2019/6

Y1 - 2019/6

N2 - This paper presents a millimeter-wave (mmW) sub-sampling PLL in 40 nm CMOS. Sub-sampling PLL reduces the in-band phase noise due to the charge pump lower than the ordinary N2× when frequency is multiplied by N. Two sub-sampling phase detectors (SSPD) and charge pumps (SSCP) are employed to cancel mixing products due to sub-sampling around the VCO output tone and to enhance loop gain. The out-of-band phase noise, dictated by the VCO phase noise, is reduced by employing a VCO consisting of transmission-line resonators, large MOSFET switches, and inverse-class-F output matching. The proposed PLL, operating at 45 GHz, achieves-40-dBc integrated phase noise (0.1 kHz-40 MHz), 3.9-dBm output power, and 2.1% DC-to-RF efficiency.

AB - This paper presents a millimeter-wave (mmW) sub-sampling PLL in 40 nm CMOS. Sub-sampling PLL reduces the in-band phase noise due to the charge pump lower than the ordinary N2× when frequency is multiplied by N. Two sub-sampling phase detectors (SSPD) and charge pumps (SSCP) are employed to cancel mixing products due to sub-sampling around the VCO output tone and to enhance loop gain. The out-of-band phase noise, dictated by the VCO phase noise, is reduced by employing a VCO consisting of transmission-line resonators, large MOSFET switches, and inverse-class-F output matching. The proposed PLL, operating at 45 GHz, achieves-40-dBc integrated phase noise (0.1 kHz-40 MHz), 3.9-dBm output power, and 2.1% DC-to-RF efficiency.

KW - CMOS

KW - Sub-sampling

KW - energy efficient

KW - low phase noise

KW - phase-locked loop

UR - http://www.scopus.com/inward/record.url?scp=85072242370&partnerID=8YFLogxK

U2 - 10.1109/RFIC.2019.8701745

DO - 10.1109/RFIC.2019.8701745

M3 - Conference contribution

AN - SCOPUS:85072242370

T3 - Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

SP - 175

EP - 178

BT - 2019 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2019

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Lee S, Takano K, Hara S, Dong R, Amakawa S, Yoshida T et al. A-40-dBc Integrated-Phase-Noise 45-GHz Sub-Sampling PLL with 3.9-dBm Output and 2.1% DC-to-RF Efficiency. In 2019 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 175-178. 8701745. (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). https://doi.org/10.1109/RFIC.2019.8701745