A 20-Gb/s Flip-Flop Circuit Using Direct-Coupled FET Logic

Makoto Shikata, Koutarou Tanaka, Hiromi T. Yamada, Hiroki Fujishiro, Seiji Nishi, Chouho Yamagishi, Masahiro Akiyama

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6 Citations (Scopus)

Abstract

A new type of direct-coupled FET logic (DCFL) flip-flop called the memory cell type flip-flop (MCFF) is presented. The MCFF operates faster than conventional DCFL flip-flops as well as enhances the advantages of DCFL such as low power consumption or high packing density. A D-flip-flop IC and a 1/8 divider IC were developed using the MCFF. These IC’s were fabricated using 0.2-μm-gate pseudomorphic inverted HEMT’s. The D-flip-flop IC is confirmed to operate up to 20 Gb/s by an originally developed measurement system. The 1/8 divider is toggled up to a maximum frequency of 25 GHz. These results prove that the MCFF enables DCFL circuits applicable not only for LSI but for SSI or MSI operating up to 20 Gb/s.

Original languageEnglish
Pages (from-to)1046-1051
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume28
Issue number10
DOIs
Publication statusPublished - 1 Jan 1993

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Shikata, M., Tanaka, K., Yamada, H. T., Fujishiro, H., Nishi, S., Yamagishi, C., & Akiyama, M. (1993). A 20-Gb/s Flip-Flop Circuit Using Direct-Coupled FET Logic. IEEE Journal of Solid-State Circuits, 28(10), 1046-1051. https://doi.org/10.1109/4.237520