0. 85 ns 1Kb BIPOLAR ECL RAM.

Hiroshi Miyanaga, Shinsuke Konaka, Yousuke Yamamoto, Tetsushi Sakai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Abstract

A 1Kb ECL RAM with an address access time of 0. 85 ns and a power dissipation of 950 mW has been developed. Such performance is achieved using SST technology with 1 mu m rule and high speed circuit design. The emitter width of the transistor is 0. 5 mu m and the cutoff frequency is 12. 4 GHz at V//C//E equals 3 V. The minimum metallization pitch is 3 mu m in the first layer and 6 mu m in the second layer.

Original languageEnglish
Title of host publicationConference on Solid State Devices and Materials
PublisherBusiness Cent for Academic Soc Japan
Pages225-228
Number of pages4
ISBN (Print)4930813077
Publication statusPublished - 1 Dec 1984

Publication series

NameConference on Solid State Devices and Materials

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Miyanaga, H., Konaka, S., Yamamoto, Y., & Sakai, T. (1984). 0. 85 ns 1Kb BIPOLAR ECL RAM. In Conference on Solid State Devices and Materials (pp. 225-228). (Conference on Solid State Devices and Materials). Business Cent for Academic Soc Japan.